When semi-conductor circuits are fabricated to manufacture such items as a computer microprocessor or other microelectronics, a certain number of failures from the total production run is expected. Typically, these failures come early or late in the life of the circuit. FIG. 1 shows a graph 10 of the number of expected failures over a period of time. The curve is commonly referred to as a xe2x80x9cbathtub curvexe2x80x9d. It shows three distinct regions: the xe2x80x9cinfant stagexe2x80x9d 12, the xe2x80x9coperational life stagexe2x80x9d 14; and the xe2x80x9cold age stagexe2x80x9d 16. During the infant stage 12, the number of failures maybe high and they decrease in number rapidly as the curve moves in the operational life stage 14. While in the operational stage 14, the number of failures falls to practically zero until the curve moves in the old age stage 16. Once in the old age stage 16, the number of failures begins the increase rapidly as the product""s effective life expires.
A goal of manufacturers is to get a product over the infant stage 12 quickly in order to weed out defects prior to shipment to the customer. In the case of semi-conductor circuits, this goal is accomplished by a procedure called xe2x80x9cburn-inxe2x80x9d. The procedure includes subjecting the circuit to stresses such as elevated temperatures and supply voltages as a technique of accelerating the operational life. For example, some semi-conductors have an infant stage that could last as long as 3-4 years of normal operation, while the operational life may last as long as 10 years. Obviously in such a case, a successful burn-in procedure must accelerate the time frame of the bathtub curve. As a result, a standard burn-in process can last about 36-48 hours. The net result is 48 hours in a burn-in procedure can simulate four years of normal operation and thereby greatly increase product reliability for the customer.
FIG. 2 shows a cross-sectional view of a prior art N-type metal oxide semi-conductor field effect transistor (N-type MOSFET). This type of transistor is devices. The transistor includes a gate 26 region, a source 28 region, and a drain 30 region. These regions are located in an architectural layer 32 of P-type material. This P layer 32 further overlays a conductive substrate 34 of doped P+ type material. This P+ substrate 34 is connected to the source voltage (Vss) 38 for the circuit. The source 28, the gate 26, and the drain 30 are each provided with a separate metallic lead 22a, 22b, 22c respectively. Each lead 22a, 22b, 22c is connected to its respective region 28, 26, 30 through a conductive contact 24a, 24b, 24c. Finally, the source 28 and drain 30 are isolated from other elements of the circuit by respective field oxide regions 36a, 36b. These regions 36a, 36b are made of a non-conductive material which prevents the transfer of any transient currents outside the transistor 20.
During normal operation, a positive voltage is applied to the gate 26 from its metallic lead 22b. This effectively turns the transistor 20 xe2x80x9conxe2x80x9d and current flows through the device. In order to turn the transistor on, the voltage applied to the gate 26 must be sufficient to overcome the threshold voltage (Vt) that is an inherent characteristic of the device. As the name implies, the threshold voltage is the point where the device switches from the xe2x80x9coffxe2x80x9d state to the xe2x80x9conxe2x80x9d state and vice-versa. Another characteristic of the device is the leakage or standby current. This is the current that normally flows through the device when it is in the xe2x80x9coffxe2x80x9d state. The threshold voltage and the leakage current have an exponential relationship.
In current circuit design trends, the threshold voltage of semi-conductor devices is being reduced as much as possible to increase the speed of the circuit. While this technique is successful in achieving performance gains, it causes difficulties during the burn-in procedure when the temperatures are increased and the supply voltage may be increased as much as 50% above normal levels. The stresses of burn-in have the effect of increasing the leakage current to unacceptable levels. The solution has been to back off on performance improvements by raising the threshold voltages in order to hold leakage current to acceptable levels during the burn-in procedure.
In some aspects the invention relates to a method for conducting a burn-in procedure for a semi-conductor device comprising: applying a burn-in procedure stress to the semi-conductor device; and applying a negative back-bias voltage to the semi-conductor device.
In an alternative embodiment, the invention relates to a method for conducting a burn-in procedure for a semi-conductor device comprising: step for applying a burn-in procedure stress to the semi-conductor device; and step for applying a negative back-bias voltage to the semi-conductor device.
Advantages of the invention may include, one or more of the following. There is no reduction in performance characteristics of semi-conductors due to leakage current constraints during the burn-in procedure. No alterations of existing statistical reliability baselines are necessary due to modifications in burn-in procedures to accommodate leakage current constraints.